Implementing Watchdog's in FPGA's

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Wednesday, July 11, 2007

Implementing Watchdog's in FPGA's

In the past I have written about the merits of incorporating a watchdog timer in your product. A watchdog protects a computer from 'locking up'. There is another way to look at this solution. A simple computer is a single sequential state machine (yes, there are multi-core computers) and a watchdog can protect that state machine from getting into unforeseen states, or dwelling in known states for too long, ... and much more.

The question I propose, is how do you protect an FPGA? An FPGA is unlike a micro-controller or DSP. It is processing many different inputs in parallel. There may be many state machines going at once. Do you implement a watchdog timer for every state machine? That solution may be untenable for all but the most rigorous designs (translation: too much work!).

I already think I know part of the solution. It should be to cause a system wide reset should any of the state machines get into an unforeseen state. That shouldn't be too difficult to implement.

I have some other thoughts on this that I will share in an upcoming lab note. I plan on implementing some of these idea in my next project here at my Hauppauge based laboratory. I will report back my success (or failures).

The project will be successful if I am able to protect the design from unforeseen input without 'significant programming effort' and achieve 'significant benefit'. Implementing the watchdog should not add more than 5% to the development effort. The process or development effort should also be mechanical and repeatable. In fact, there is no reason why this could not be incorporated directly into the FPGA development tool and be transparant to the programmer.

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